Energy-efficient Hardware for Artificial Intelligence

The Competition: ECG Data is Automatically Analyzed with the Lowest Energy Consumption

Within the framework of a pilot innovation competition of the Federal Ministry of Education and Research (BMBF), a system for the reliable detection of atrial fibrillation is to be developed which is to be as energy-efficient as possible. The focus is on the hardware that will be developed specifically for this task. So-called Field Programmable Gate Arrays (FPGA) are prescribed as the hardware platform for this competition. FPGAs are special chips whose circuits can be reconfigured during operation and thus allow the fast realization of any circuit on concrete hardware.

The Fraunhofer ITWM was selected together with our partner, the Microelectronic Systems Design Research Group at the Rheinland-Pfälzische Technische Universität Kaiserslautern-Landau (RPTU), to participate in this competition.

Our Approach: Energy-Efficient Hardware Starts with the Algorithm

For this competition, we choose a holistic approach that looks at the application and the hardware at the same time, thus achieving the optimal execution of an optimal algorithm. The project name HALF - Holistic AutoML for FPGAs - reflects the core aspect of our approach.

An important finding is that the AI model not only determines the quality of detection, but also very decisively the energy consumption on the hardware. Instead of focusing only on the hardware and relying on known AI models, we use state-of-the-art methods to automatically search for AI models. In doing so, we combine this search with hardware-specific criteria so that we can find optimal models for the underlying hardware platform.

The difficulty is to find a balance between a lightweight and energy-efficient model on the one hand and its reliability and robustness on the other.

The software tools we have developed enable an almost fully automated search for the best design in a multi-stage process. Starting with the ECG data set, so-called Auto-ML (Automated Machine Learning) methods search for the best model for the given data. During the search, both unimportant parts of the model are avoided and hardware-specific criteria that determine energy consumption are taken into account. An optimal design for the FPGA platform is generated for the model thus found. Finally, the FPGA is configured and is then capable of automatically evaluating ECG data.

Our Project Partner:

The Microelectronic Systems Design Research Group at the RPTU Kaiserslautern provides the know-how to map the AI models to the hardware. In particular, the hardware architecture generation methods developed by the EMS Group are used to exploit the full potential of the FPGA hardware platform.